1. Field of the Invention
The present invention relates to a method and device for optimizing a logic circuit represented by a circuit diagram or hardware description language, and more particularly to a method and device for optimizing a logic circuit having a hierarchical structure.
2. Description of the Related Art
The automatic generation of a logic circuit from information such as hardware description language is carried out so as to satisfy constraints such as delay time or available area for packaging, i.e., limit values. In optimization that takes as its object a logic circuit having a hierarchical structure including a plurality of hierarchies, the target limit values of the delay time or available area for packaging are determined in advance.
In a prior art method to optimize a logic circuit with a predetermined delay time as the target, limit values are first established with due consideration given to the delay between flip-flops and input terminals of each hierarchy as well as to the delay between the flip-flops and output terminals, the established limit values are given to the input terminal and output terminal of each hierarchy, and the optimization process is performed for each hierarchy. With this method, the optimization of the logic circuit of each hierarchy lead to the optimization of the entire circuit.
However, since the delay time limit values were determined by taking into consideration the flip-flops in each hierarchy in the optimization method of the prior art, these limit values were meaningless if paths existed that did not pass through the flip-flops in a hierarchy, and normal optimization could not be carried out. For these paths, the hierarchies were manually restructured and the limit values were again determined.
It is an object of the present invention to provide a method and device for easy and proper optimization of a logic circuit of hierarchical structure that includes at least one flip-flop.
In the present invention, target delay values, which are the limit values of delay times, are determined in advance. The logic circuit is then modified to a hierarchical structure of a plurality of hierarchical circuits that take as interfaces: the input terminals of flip-flops, the external input terminals of the logic circuit, and the external output terminals of the logic circuit. Each of the hierarchical circuits is then optimized such that the delay times are less than or equal to the target delay values.
The hierarchical structure of the logic circuit that is the object of optimization is thus modified such that the input terminals of flip-flops become the interfaces of each hierarchical circuit, to thereby execute the optimization process after establishing a state in which there are no paths that do not pass through flip-flops in each hierarchical circuit.
According to another aspect of the present invention, target delay values, which are the limit values of delay times, are determined in advance, following which the flip-flops included in the logic circuit are extracted. The logic circuit is then traced in the direction that is opposite the flow of signals from an external output terminal of the logic circuit or the input of an extracted flip-flop until reaching an external input terminal of the logic circuit or another flip-flop. The hierarchical structure of the logic circuit is then altered to a structure composed of hierarchical circuits that include the logic elements that were passed through and the flip-flops that were reached. Hierarchical circuits that include the same flip-flops are next joined. Finally, each of the hierarchical circuits is optimized such that the delay times are equal to or less than the target delay values.
The logic circuit optimization device according to the present invention comprises a limit value storage means, a hierarchy restructuring means, and a logic optimization execution means.
The limit value storage means stores in advance the target delay values, which are the limit values of delay times. The hierarchy restructuring means restructures a logic circuit into a hierarchical structure composed a plurality of hierarchical circuits that take as interfaces the input terminals of flip-flops, the external input terminals of the logic circuit, and the external output terminals of the logic circuit. The logic optimization execution means optimizes each hierarchical circuit such that the delay times are equal to or less than the target delay values.
According to another aspect of the invention, a logic circuit optimization device comprises a limit value storage means, a flip-flop extraction means, a hierarchy modification means, a hierarchical circuit merge means, and a logic optimization execution means.
The limit value storage means stores in advance target delay values, which are the limit values of the delay times. The flip-flop extraction means extracts flip-flops included in the logic circuit. The hierarchy modification means traces the logic circuit in the direction that is opposite the flow of signals from an external output terminal of the logic circuit or the input terminal of an extracted flip-flop until reaching an external input terminal of the logic circuit or another flip-flop and modifies the hierarchical structure of the logic circuit to a structure composed of hierarchical circuits that are each constituted by the logic elements that were passed through and the flip-flops that were reached. The hierarchical circuit merge means joins hierarchical circuits that include the same flip-flop. The logic optimization execution means optimizes each of the hierarchical circuits such that the delay times are equal to or less than the target delay values.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with references to the accompanying drawings which illustrate examples of the present invention.